High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits

MLA

Hung-Chun Chen, et al. “High Performance and Low Power Monolithic Three-Dimensional Sub-50 Nm Poly Si Thin Film Transistor (TFTs) Circuits.” Scientific Reports, vol. 7, May 2017. EBSCOhost, widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edsair&AN=edsair.doi.dedup.....5a9245fb6984f13052689370b4205ab7&authtype=sso&custid=ns315887.

APA

Hung-Chun Chen, Ming-Hsuan Kao, Yi-Ling Jian, Tsung-Ta Wu, Chang-Hong Shen, Chih-Chao Yang, Chiu-Hao Chen, Chiung-Chih Hsu, Kun-Lin Lin, Jia-Min Shieh, Tung-Ying Hsieh, Yu-Lun Chueh, Jie-Yi Yao, Wei-Sheng Lin, & Wen-Hsien Huang. (2017). High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits. Scientific Reports, 7.

Chicago

Hung-Chun Chen, Ming-Hsuan Kao, Yi-Ling Jian, Tsung-Ta Wu, Chang-Hong Shen, Chih-Chao Yang, Chiu-Hao Chen, et al. 2017. “High Performance and Low Power Monolithic Three-Dimensional Sub-50 Nm Poly Si Thin Film Transistor (TFTs) Circuits.” Scientific Reports 7 (May). http://widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edsair&AN=edsair.doi.dedup.....5a9245fb6984f13052689370b4205ab7&authtype=sso&custid=ns315887.