A high performance single chip processing unit for parallel processing and data acquisition systems

Authors :: Raffaele Tripiccione
W. Tross
Simone Cabasino
A. Fucci
Pierluigi Paolucci
C. Battista
M. Torelli
F. Marzano
A. Lai
R. Borgognoni
J. Pech
R. Sarno
G. M. Todesco
N. Cabibbo
G. Bastianello
Piero Vicini
Publication Year :: 1993
Abstract: We present a new VLSI integer scalar processor, intended to be used primarily as the controller of the APE100 massively parallel processor. Its open and flexible architecture indicates a potential for use in other HEP applications, such as front-end processing or data readout.

Subjects :: Very-large-scale integration
Physics
Nuclear and High Energy Physics
Scalar processor
business.industry
Controller (computing)
Integrated circuit
law.invention
Computer Science::Hardware Architecture
Data acquisition
Parallel processing (DSP implementation)
law
business
Instrumentation
Massively parallel
Computer hardware
Integer (computer science)

Tools