Extending DaCe to support the Scalable Vector Extension

SIMD is characterized by operating on arrays or vectors of data instead of individual scalar data elements. Typical systems implement this design with special vector registers and instructions that allow operating on each element in the vector at once. The Scalable Vector Extension (SVE) is a vector instruction set proposed by ARM and purposely designed for High-Performance Computing. It is an attractive target for the DaCe framework that allows optimizing code in a platform-independent, data-centric intermediate representation before exporting it to a specific platform. However, due to SVE being a novel and unparalleled vector instruction set, DaCe lacks its support. We propose a vectorization transformation and code generator capable of generating SVE instructions from an intermediate representation. Our results demonstrate that our transformation and code generation are on par and, in some cases, outperform the existing auto-vectorization in Fujitsu's C++ compiler. We anticipate our extension to be the starting point for a more complex framework that supports numerous unique capabilities of SVE, for example, the prefetching mechanism. Furthermore, writing efficient SVE code is more challenging than initially expected. We suggest additional research to find explicit weaknesses in auto-vectorization that DaCe and our framework can overcome.