Hardware-In-The Loop Emulation for Agile Co-Design of Parallel Ultra-Low Power IoT Processors

Simulation of Computing Systems plays a crucial role in state-of-the-art design validation and optimization methodologies. Traditionally, Register Transfer-Level (RTL) simulation is a well-established approach to perform performance analysis as well as functional validation. However, more agile simulation and emulation methodologies are required for architectural exploration and optimization, given the always increasing complexity of parallel processors, including those designed for ultra-low power IoT end-nodes. Architectural simulators are the most commonly used tools to explore parallel computing architectures. Nevertheless, they are often not accurate enough to identify and quantify system-level performance bottlenecks, such as access to external peripherals or contentions on shared resources. In this context, FPGA logic emulation is gaining increasing popularity. In this paper, we exploit and introduce a “Hardware-in-the-loop” framework that eases HW/SW co-design of Parallel-ultra-low power IoT processors by enabling the analysis of the full cyber-physical loop from sensing to actuation. We use the proposed methodology to carry out $\mu$ Architectural optimizations and to demonstrate performance improvements on two real-life end-to-end applications with full hardware in the loop emulation. Our results show that we can run workloads on real-life applications more than 3’000 times faster than cycle-accurate RTL, and with speed similar to instruction accurate simulators but with full cycle accuracy.