Topology-related upset mechanisms in design hardened storage cells

Authors :: Michael Nicolaidis
V.T. Tran
R. Koga
K. Clark
Steven C. Moss
Stephen LaLumondiere
Raoul Velazco
T. Calin
Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA)
Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)
iROc Technologies (IROC TECHNOLOGIES)
Cadence Connection-EDA Consortium-FSA-Cubic Micro
The Aerospace Corporation
US. Air Force (SMCIAXE)
US. Air Force
Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA)
Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)
The Aerospace Corporation (THE AEROSPACE CORPORATION)
Source :: RADECS-97
Publication Year :: 1998
Publisher :: HAL CCSD, 1998.
Abstract: The SEU hardness of a new CMOS storage cell based on latch redundancy has been analyzed using a laser beam simulation. We detected and investigated topology-dependent upset mechanisms due to charge collection at two sensitive nodes using a laser excitation between the nodes. Compact upset-immune device topologies are proposed, using spacing and isolation techniques for simultaneously sensitive node pairs, to achieve high immunity levels required in critical applications.

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