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Fault tolerant permutation mapping in multistage interconnection network

Authors :
Ujjwal Maulik
Shankar P. Bhattacharyya
Sanghamitra Bandyopadhyay
Source :
Scopus-Elsevier
Publication Year :
2000
Publisher :
Elsevier BV, 2000.

Abstract

An efficient scheme for fault tolerant mapping of permutations is designed. The proposed algorithm uses extra passes through the network, instead of additional hardware.

Subjects

Subjects :
Scheme (programming language)
Interconnection
Computer science
Distributed computing
Fault tolerance
Parallel computing
Stuck-at fault
Computer Science::Hardware Architecture
Permutation
Hardware and Architecture
Routing (electronic design automation)
Computer Science::Operating Systems
computer
Software
computer.programming_language

Details

ISSN :
13837621
Volume :
46
Database :
OpenAIRE
Journal :
Journal of Systems Architecture
Accession number :
edsair.doi.dedup.....457e7dda9f21a07fab6b7457216c48f9
Full Text :
https://doi.org/10.1016/s1383-7621(98)00078-2
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