Integration of Strain Free III–V Quantum Dots on Silicon

The great interest in the implementation of GaAs quantum nanostructures (QNs) on silicon substrates is mainly due to the possibility of integrating specialized high efficiency optoelectronic and photonic devices on the existing complementary metal-oxide semiconductor technology developed on Si. This would allow the realization of specialized III–V devices such as nanoemitters and intersubband detectors directly embedded with a large number of existing Si devices. Of particular, technological interest is the possibility of carrying out the III–V device fabrication after the integrated circuit has been already realized, i.e., as a back-end process. In this case, the compatibility with the underlying integrated circuit is possible only imposing strict constraints on thermal budget for growth and processing of the epilayer.