High-precision time-to-digital converter in a FPGA device

The construction and design process of a highresolution time-interval measuring system implemented in a SRAM-based FPGA device is discussed in this paper. The TDC can increase the precision on the measurement by interpolating time within the system clock cycle. A two step phase interpolation has been constructed, one based on the phase information delivered by the VIRTEX-5 Digital Clock Manager (DCM) and thus providing a fine time, a second level phase interpolation was based on carry lines thus delivering an hyper fine time measurement. We have designed and built a PCB hosting a Virtex-5 Xilinx FPGA. The board we have designed provides 7 TDC channels. The number of channels turns out to be limited by the number of input connectors inserted on the board and not on the code density on the FPGA. The range is in principle slightly longer than 1 day (127941 sec), but our tests are preliminary and have been made on intervals less than 20 μsec. In this range we have measured a resolution which is better than 55 psec for the time interval on a single channel in single and multi-hit mode.