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OmpSs@FPGA framework for high performance FPGA computing
- Source :
- UPCommons. Portal del coneixement obert de la UPC, Universitat Politècnica de Catalunya (UPC)
- Publication Year :
- 2021
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 2021.
-
Abstract
- This paper presents the new features of the OmpSs@FPGA framework. OmpSs is a data-flow programming model that supports task nesting and dependencies to target asynchronous parallelism and heterogeneity. OmpSs@FPGA is the extension of the programming model addressed specifically to FPGAs. OmpSs environment is built on top of Mercurium source to source compiler and Nanos++ runtime system. To address FPGA specifics Mercurium compiler implements several FPGA related features as local variable caching, wide memory accesses or accelerator replication. In addition, part of the Nanos++ runtime has been ported to hardware. Driven by the compiler this new hardware runtime adds new features to FPGA codes, such as task creation and dependence management, providing both performance increases and ease of programming. To demonstrate these new capabilities, different high performance benchmarks have been evaluated over different FPGA platforms using the OmpSs programming model. The results demonstrate that programs that use the OmpSs programming model achieve very competitive performance with low to moderate porting effort compared to other FPGA implementations. This work has received funding from EuroEXA project (European Union’s Horizon 2020 Research and Innovation Programme, under grant agreement No 754337), from Spanish Government (projects PID2019-107255GB and SEV-2015- 0493, grant BES-2016-078046), and Generalitat de Catalunya (contracts 2017-SGR-1414 and 2017-SGR-1328).
- Subjects :
- Computer science
02 engineering and technology
Parallel computing
computer.software_genre
Porting
Theoretical Computer Science
Runtime system
Parallel architectures
High-level synthesis
0202 electrical engineering, electronic engineering, information engineering
Field-programmable gate array
Informàtica::Arquitectura de computadors::Arquitectures paral·leles [Àrees temàtiques de la UPC]
FPGA
Compilers (Computer programs)
Matrius de portes programables per l'usuari
Parallel processing (Electronic computers)
Task-based programming models
Processament en paral·lel (Ordinadors)
Compiladors (Programes d'ordinador)
Local variable
Field programmable gate arrays
Reconfigurable computing
Reconfigurable hardware
020202 computer hardware & architecture
Computational Theory and Mathematics
Hardware and Architecture
Programming paradigm
Compiler
computer
Software
Subjects
Details
- Database :
- OpenAIRE
- Journal :
- UPCommons. Portal del coneixement obert de la UPC, Universitat Politècnica de Catalunya (UPC)
- Accession number :
- edsair.doi.dedup.....410fc3f80c5fdba618e2642e937c9163