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FPGA-based Systems for Evolvable Hardware

Authors :
Lambert, C
Kalganova, T
Stomeo, E
Source :
Conference of the World Academy of Science, Engineering and Technology
Publication Year :
2007
Publisher :
Zenodo, 2007.

Abstract

Since 1992, year where Hugo de Garis has published the first paper on Evolvable Hardware (EHW), a period of intense creativity has followed. It has been actively researched, developed and applied to various problems. Different approaches have been proposed that created three main classifications: extrinsic, mixtrinsic and intrinsic EHW. Each of these solutions has a real interest. Nevertheless, although the extrinsic evolution generates some excellent results, the intrinsic systems are not so advanced. This paper suggests 3 possible solutions to implement the run-time configuration intrinsic EHW system: FPGA-based Run-Time Configuration system, JBits-based Run-Time Configuration system and Multi-board functional-level Run-Time Configuration system. The main characteristic of the proposed architectures is that they are implemented on Field Programmable Gate Array. A comparison of proposed solutions demonstrates that multi-board functional-level run-time configuration is superior in terms of scalability, flexibility and the implementation easiness.<br />{"references":["H. de Garis. \"Evolvable Hardware: Principles and Practice\".\nCommunications of the Association for Computer Machinery (CACM\nJournal). August 1997.","X. Yao, T. Higuchi. \"Promises and challenges of evolvable hardware\"\nIEEE Trans. Systems, Man and Cybernetics, Part C, vol. 29, Pages. 87 -\n97, February 1999.","D. E. Goldberg. Genetic algorithm in search, optimization and machine\nlearning. Addison-Wesley Publishing Company, Incorporated, Reading,\nMassachusetts, 1989.","N. J. Macias. \"The PIG paradigm: the design and use of a massively\nparallel fine grained self-reconfigurable infinitely scalable architecture\".\nProceedings of the First NASA/DoD Workshop on, 19-21. pp: 175-180.\n1999.","A. Stoica, D. Keymeulen, D. Vu, R. Zebulum, I. Ferguson, T. Daud, T.\nArsian, G. Xin. \"Evolutionary recovery of electronic circuits from\nradiation induced faults\". Evolutionary Computation, 2004. CEC2004.\nCongress on, Volume: 2, 19-23. pp: 1786-1793. Vol.2. 2004.","J. Langeheine, K. Meier, J. Schemmel, M. Trefzer. \"Intrinsic evolution\nof digital-to-analog converters using a CMOS FPTA chip\". Evolvable\nHardware, 2004. Proceedings. 2004 NASA/DoD Conference on, 24-26.\npp: 18-25. 2004.","I. Kajitani, et al. \"A gate-level EHW chip: Implementing GA operations\nand reconfigurable hardware on a single LSI\". (Proc. of Second\nInternational Conference on Evolvable Systems: From Biology to\nHardware (ICES1998)). Springer Verlag. pp. 1-12.","V. Baumgarte, F. May, A N├╝ckel, M. Vorbach, and M. Weinhardt.\n\"PACT XPP - A self-Reconfigurable Data Processing Architecture\".\nPresented at ERSA'01, Las Vegas, NV, (c) CSREA Press. 2001.","A. Thompson. \"Exploring Beyond the Scope of Human Design:\nAutomatic generation of FPGA configurations through artificial\nevolution.\" 8th Annual Advanced PLD & FPGA Conference 1998.\n[10] L. Sekanina, S. Friedl. \"On Routine Implementation of Virtual\nEvolvable Devices Using COMBO6\". In: Proc. of the 2004 NASA/DoD\nConference on Evolvable Hardware, Los Alamitos, US, ICSP. pp. 63-70,\nISBN 0-7695-2145-2. 2004.\n[11] M. Iwata, I. Kajitani, Y. Liu, N. Kajihara, T. Higuchi. \"Implementation\nof a Gate-Level Evolvable Hardware Chip.\" Evolvable Systems: From\nBiology to Hardware. Lecture Notes in Computer Science 2210 (Proc. of\nICES2001). Springer Verlag. pp. 38-49. 2001.\n[12] G. Tufte, P. C. Haddow. \"Identification of functionality during\ndevelopment on a virtual Sblock FPGA\". Evolutionary Computation,\n2003. CEC '03. The 2003 Congress on. Volume: 1. pp. 8-12. Dec. 2003.\n[13] I. Rechenberg, \"Evolution Strategy\", in J. Zurada, R. Marks II, and C.\nRobinson (Eds.), Computational Intelligence: Imitating Life, 1994, pp.\n147-159.\n[14] J. Torresen, J. W. Bakke and L. Sekanina. \"Recognizing Speed Limit\nSign Numbers by Evolvable Hardware.\" In proc. of 8th International\nConference on Parallel Problem Solving from Nature (PPSN VIII). UK.\n2004.\n[15] Xilinx. \"Virtex-E 1.8V FPGA Complete Data Sheet\". 14/3/2003.\n[16] Xilinx. \"Spartan-II 2.5V FPGA Complete Data Sheet\". 9/3/2003.\n[17] T. Kalganova, J.F. Miller. \"Evolving more efficient digital circuits by\nallowing circuit layout evolution and multi-objective fitness\". Proc. of\nthe First NASA/DoD Workshop on Evolvable Hardware pp. 54-65.\n[18] Xilinx. \"XAPP151 - Virtex Series Configuration Architecture User\nGuide\", v1.6. 24/3/2003.\n[19] W. Huang, S. Mitra, E. J. McCluskey, \"Fast Run-Time Fault Location in\nDependable FPGA-Based Applications\", DFT 2001.\n[20] Xilinx. \"Virtex-II Platform FPGA User Guide\", v1.9. pp. 206-214.\n05/8/2004.\n[21] L. Sekanina, \"Towards Evolvable IP Cores for FPGAs\". In: Proc. of\nThe 2003 NASA/DoD Conference on Evolvable Hardware, Los\nAlamitos, US, ICSP, pp. 145-154, ISBN 0-7695-1977-6. 2003.\n[22] http://unit.aist.go.jp/asrc/asrc-5/en/overview.html"]}

Details

Language :
English
Database :
OpenAIRE
Journal :
Conference of the World Academy of Science, Engineering and Technology
Accession number :
edsair.doi.dedup.....37a085049ad4809883d6f6218c5e41d3
Full Text :
https://doi.org/10.5281/zenodo.1075382