Modeling and formal control of partial dynamic reconfiguration

This paper introduces an approach for the safe design and modeling of dynamically reconfigurable FPGA based Systems-on-Chip. This approach is carried out in a design framework, Gaspard2, dedicated to high-performance embedded systems modeling using the OMG standard profile UML/MARTE. Information employed by the reconfiguration mechanism is identified to be extracted from MARTE models in order to synthesize a controller using a formal technique which significantly simplifies the correct design of reconfiguration control. This methodology is then demonstrated in a case study.