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Static Probabilistic Timing Analysis in Presence of Faults

Authors :
Giovanni Beltrame
Luca Santinelli
Jérôme Hugues
Chao Chen
Institut Supérieur de l'Aéronautique et de l'Espace - ISAE-SUPAERO (FRANCE)
Office National d'Etudes et Recherches Aérospatiales - ONERA (FRANCE)
Département Traitement de l'Information et Modélisation - DTIM (Toulouse, France)
Source :
SIES
Publication Year :
2016

Abstract

Accurate timing prediction for software execution is becoming a problem due to the increasing complexity of computer architecture, and the presence of mixed-criticality workloads. Probabilistic caches were proposed to set bounds to Worst Case Execution Time (WCET) estimates and help designers improve system resource usage. However, as technology scales down, system fault rates increase and timing behavior is affected. In this paper, we propose a Static Probabilistic Timing Analysis (SPTA) approach for caches with evict-on-miss random replacement policy using a state space modeling technique, with consideration of fault impacts on both timing analysis and task WCET. Different scenarios of transient and permanent faults are investigated. Results show that our proposed approach provides tight probabilistic WCET (pWCET) estimates and as fault rate increases, the timing behavior of the system can be affected significantly.

Details

Language :
English
Database :
OpenAIRE
Journal :
SIES
Accession number :
edsair.doi.dedup.....1d100601e139f34cfad7246c5b2021de