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Modeling and Evaluation of Application-Aware Dynamic Thermal Control in HPC Nodes

Authors :
Luca Benini
Daniele Cesarini
Andrea Bartolini
Alma Mater Studiorum Università di Bologna [Bologna] (UNIBO)
Eidgenössische Technische Hochschule - Swiss Federal Institute of Technology [Zürich] (ETH Zürich)
Michail Maniatakos
Ibrahim (Abe) M. Elfadel
Matteo Sonza Reorda
H. Fatih Ugurdag
José Monteiro
Ricardo Reis
TC 10
WG 10.5
Cesarini D.
Bartolini A.
Benini L.
Source :
IFIP Advances in Information and Communication Technology, 25th IFIP/IEEE International Conference on Very Large Scale Integration-System on a Chip (VLSI-SoC), 25th IFIP/IEEE International Conference on Very Large Scale Integration-System on a Chip (VLSI-SoC), Oct 2017, Abu Dhabi, United Arab Emirates. pp.198-219, ⟨10.1007/978-3-030-15663-3_10⟩, VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things ISBN: 9783030156626, VLSI-SoC (Selected Papers)
Publication Year :
2017
Publisher :
HAL CCSD, 2017.

Abstract

International audience; As side effects of the end of Dennard’s scaling, power and thermal technological walls stand in front of the evolution of supercomputers towards the exaflops era. Energy and temperature walls are big challenges to face for assuring a constant grow of performance in future. New generation architectures for HPC systems implement HW and SW components to address energy and thermal issues for increasing power and efficient computing in scientific workload. In thermal-bound HPC machines, workload-aware runtimes can leverage hardware knobs to guarantee the best operating point in term of performance and power saving without violating thermal constraints.In this paper, we present an integer-linear programming formulation for job mapping and frequency selection for thermal-bound HPC nodes. We use a fast solver and workload traces extracted from a real supercomputer to test our methodology. Our runtime is integrated into the MPI library, and it is capable of assigning high-performance cores to performance-critical processes. Critical processes are identified at execution time through a mathematical formulation, which relies on the characterization of the application workload and on the global synchronization barriers. We demonstrate that by combining long and short horizon predictions with information on the critical processes retrieved from the programming model, we can drastically improve the performance of the target application w.r.t. state-of-the-art DTM solutions.

Details

Language :
English
ISBN :
978-3-030-15662-6
ISBNs :
9783030156626
Database :
OpenAIRE
Journal :
IFIP Advances in Information and Communication Technology, 25th IFIP/IEEE International Conference on Very Large Scale Integration-System on a Chip (VLSI-SoC), 25th IFIP/IEEE International Conference on Very Large Scale Integration-System on a Chip (VLSI-SoC), Oct 2017, Abu Dhabi, United Arab Emirates. pp.198-219, ⟨10.1007/978-3-030-15663-3_10⟩, VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things ISBN: 9783030156626, VLSI-SoC (Selected Papers)
Accession number :
edsair.doi.dedup.....14aef0d2177eb508f9fbac59bbf4db4e
Full Text :
https://doi.org/10.1007/978-3-030-15663-3_10⟩