An efficient memristor crossbar architecture for mapping Boolean functions using Binary Decision Diagrams (BDD)

The memristor is considered as the fourth fundamental circuit element along with resistor, capacitor and inductor. It is a two-terminal passive circuit element whose resistance value changes based on the amount of charge flowing through it. Another property of the memristor is that its resistance change is non-volatile in nature, and hence can be used for non-volatile memory applications. Researchers have been exploring memristors from various perspectives such as logic design and storage applications. In this paper, a slicing crossbar architecture for the efficient mapping of Boolean functions is proposed which exploits gate level parallelism using the memristor aided logic (MAGIC) design style. A Boolean function is first represented as a Binary Decision Diagram (BDD). The BDD nodes are expressed as netlists of NOR and NOT gates, and are mapped to the proposed slicing crossbar architecture with parallel node evaluation where possible. This is the first approach that combines BDD-based synthesis with MAGIC gate evaluation on memristor crossbar, while at the same time avoiding crossbar-related problems using a slicing architecture. Experimental evaluations on standard benchmark functions show considerable improvement in the solutions. This work was supported fully by the Department of Science and Technology, Government of India, for the project “Development of CAD Tools for Synthesis, Optimization and Verification of Digital Circuits using Memristors” (Grant No. INT/AUSTRIA/BMWF/P-02/2017), and by the Austrian Agency for International Cooperation in Education and Research (OeAD, Grant No. IN 08/2017).