Formal Semantics of VHDL Timing Constructs

Authors :: Ashraf Salem
Dominique Borrione
TIM3
Institut National Polytechnique de Grenoble (INPG)-Université Joseph Fourier - Grenoble 1 (UJF)-Centre National de la Recherche Scientifique (CNRS)
Université Ain Shams
Torella, Lucie
Source :: VHDL for Simulation, Synthesis and Formal Proofs of Hardware, VHDL for Simulation, Synthesis and Formal Proofs of Hardware, kluwer academic publishers, pp.195-206, 1970, 0.7923.9253.1, Second European Conference on VHDL Methods, Second European Conference on VHDL Methods, Sep 1991, Stockholm, France. pp.276-281, The Kluwer International Series in Engineering and Computer Science ISBN: 9781461365822
Publication Year :: 1970
Publisher :: HAL CCSD, 1970.
Abstract: The aim of the work presented here is to enlarge the subset of VHDL which can be manipulated by formal verification tools by including the timing constructs. In this paper we give formal semantics for these constructs. And, we prove, partially, the equivalence between these semantics and the informal operational semantics of the language as defined in the VHDL language reference manual. Also, we show how these semantics can establish a basis for the construction of formal timing verifiers.

Language :: English
ISBN :: 978-1-4613-6582-2
ISBNs :: 9781461365822
Database :: OpenAIRE
Journal :: VHDL for Simulation, Synthesis and Formal Proofs of Hardware, VHDL for Simulation, Synthesis and Formal Proofs of Hardware, kluwer academic publishers, pp.195-206, 1970, 0.7923.9253.1, Second European Conference on VHDL Methods, Second European Conference on VHDL Methods, Sep 1991, Stockholm, France. pp.276-281, The Kluwer International Series in Engineering and Computer Science ISBN: 9781461365822
Accession number :: edsair.doi.dedup.....0a8b7d1875d8e18b1ea35247bed2feb4

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