Back to Search Start Over

VDS and VGS Depolarization Effect on SiC MOSFET Short-Circuit Withstand Capability Considering Partial Safe Failure-Mode

Authors :
Jean-Michel Reynes
Wadia Jouha
Yazan Barazi
Frédéric Richardeau
IRT Saint Exupéry - Institut de Recherche Technologique
Convertisseurs Statiques (LAPLACE-CS)
LAboratoire PLasma et Conversion d'Energie (LAPLACE)
Université Toulouse III - Paul Sabatier (UT3)
Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP)
Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3)
Université Fédérale Toulouse Midi-Pyrénées
Source :
Energies, Vol 14, Iss 7960, p 7960 (2021), Energies; Volume 14; Issue 23; Pages: 7960, Energies, Energies, MDPI, 2021, Invited Paper-Special Issue Safety Design and Management of Power Devices including Gate-Drivers, ⟨10.3390/en14237960⟩
Publication Year :
2021
Publisher :
MDPI AG, 2021.

Abstract

International audience; This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution.This paper presents a detailed analysis of 1200 V Silicon Carbide (SiC) power MOSFETexhibiting different short-circuit failure mechanisms and improvement in reliability by VDS andVGS depolarization. The device robustness has undergone an incremental pulse under differentdensity decreasing; either drain-source voltage or gate-driver voltage. Unlike silicon device, the SiCMOSFET failure mechanism firstly displays specific gradual gate-cracks mechanism and progressivegate-damage accumulations greater than 4 µs/9 J·cm−2. Secondly, a classical drain-source thermalrunaway appears, as for silicon devices, in a time greater than 9 µs. Correlations with short-circuitenergy measurements and temperature simulations are investigated. It is shown that the firstmechanism is an incremental soft gate-failure-mode which can be easily used to detect and protectthe device by a direct feedback on the gate-driver. Furthermore, it is highlighted that this newmechanism can be sufficiently consolidated to avoid the second drain-source mechanism which is ahard-failure-mode. For this purpose, it is proposed to sufficiently depolarize the on-state gate-drivevoltage to reduce the chip heating-rate and thus to decouple the failure modes. The device is muchmore robust with a short-circuit withstand time higher than 10 µs, as in silicon, no risk of thermalrunaway and with an acceptable penalty on RDS-ON.

Details

Language :
English
ISSN :
19961073
Volume :
14
Issue :
7960
Database :
OpenAIRE
Journal :
Energies
Accession number :
edsair.doi.dedup.....096a8c098b340527fb523ceb872c63cc