Design of a Reliable p-Channel LDMOS FET With RESURF Technology

High-voltage lateral diffused MOS (LDMOS) FETs have been widely developed and studied for analog application. High-temperature reverse bias (HTRB) instability is one of the largest concerns for this device in achieving high reliability guaranteeing performance stability. This paper focuses on a lower RON approach for 200 V p-channel LDMOS FET with a reduced surface electric field technique, where effectiveness of the drift profile optimization is proposed. Then, HTRB degradation phenomenon relating RON and BVOFF shift was focused on. Through the analysis via device simulation, HTRB shift phenomenon was found to be well simulated with the electron trap feature in the field oxide over the drift region, where the electron was generated by impact ionization under a high-voltage reverse bias stress condition. The technique using a metal field plate for improving impact ionization voltage with maintenance of RON is also proposed for stable p-channel LDMOS FETs that can deliver reliable and high-performance applications.