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A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration
- Source :
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 31:199-209
- Publication Year :
- 2023
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 2023.
- Subjects :
- Hardware and Architecture
Electrical and Electronic Engineering
Software
Subjects
Details
- ISSN :
- 15579999 and 10638210
- Volume :
- 31
- Database :
- OpenAIRE
- Journal :
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Accession number :
- edsair.doi...........fb480b97cd0ed8ecbcb6ada5040e5f4b