A novel low voltage and high speed CMOS charge pump circuit

A novel low voltage, high speed CMOS charge pump circuit for PLL is designed in the paper. The new structure refrains from the common spurious jump phenomenon, and is designed in N well mixed-signal Chartered 0.35μm CMOS process, simulated using Hspice. The results show the new circuit can operate under a 1V power supply, does not suffer from any waveform jitter. The output voltage has a relatively wide range, from 120mV up to 980mV. The operating frequency is 500MHz, and power consumption is low to 150μW.