Design, evaluation and application of approximate‐truncated Booth multipliers

Approximate computing provides a promising way to achieve low power design at the cost of acceptable error. As a core component in a processor, the performance of the multiplier is important. This study presents designs of approximate-truncated Booth multipliers (ATBMs) using proposed approximate modified radix-4 Booth encoders (AMBEs), approximate 4-2 compressors (ACs) and gradually truncated partial products. The accuracy of the ATBMs is adjustable with the so-called approximation factors that indicate the number of AMBEs and ACs used. The normalised mean error distance and the product of the power and delay are used to evaluate the error and the hardware performance of the multipliers. The results show that the proposed ATBMs outperform previous approximate Booth multipliers. Their validity is also shown with case studies of image processing, K-means clustering and handwritten digit recognition.