65nm Low Power (LP) SOI technology on HR substrate for WLAN and Mmwave SOCs

MLA

Christine Raynaud, et al. “65nm Low Power (LP) SOI Technology on HR Substrate for WLAN and Mmwave SOCs.” ECS Meeting Abstracts, May 2009, p. 961. EBSCOhost, https://doi.org/10.1149/ma2009-01/23/961.

APA

Christine Raynaud, Sebastien Haendler, Georges Guegan, Frederic Gianesello, Baudouin Martineau, Patricia Touret, & Nicolas Planes. (2009). 65nm Low Power (LP) SOI technology on HR substrate for WLAN and Mmwave SOCs. ECS Meeting Abstracts, 961. https://doi.org/10.1149/ma2009-01/23/961

Chicago

Christine Raynaud, Sebastien Haendler, Georges Guegan, Frederic Gianesello, Baudouin Martineau, Patricia Touret, and Nicolas Planes. 2009. “65nm Low Power (LP) SOI Technology on HR Substrate for WLAN and Mmwave SOCs.” ECS Meeting Abstracts, May, 961. doi:10.1149/ma2009-01/23/961.