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P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation

Authors :
Shi-Yu Huang
Cheng-Hung Lo
Source :
IEEE Journal of Solid-State Circuits. 46:695-704
Publication Year :
2011
Publisher :
Institute of Electrical and Electronics Engineers (IEEE), 2011.

Abstract

SRAM has been under its renovation stage recently, aiming to withstand the ever-increasing process variation as well as to support ultra-low-power applications using even subthreshold supply voltages. We present in this paper a novel P-P-N-based 10T SRAM cell, in which the latch is formed essentially by a cross-coupled P-P-N inverter pair. This type of cell can operate at a voltage as low as 285 mV while still demonstrating high resilience to process variation. Its noise margin has been elevated in not only the hold state, but also the read operations. As compared to previous 10T SRAM cells, our cell excels in particular in two aspects: 1) ultra-low cell leakage, and 2) high immunity to the data-dependent bitline leakage. The second merit makes it especially suitable for an SRAM macro with long bitlines - a property often desirable in order to achieve high density. We have fabricated and validated its performance through a 16 Kb SRAM test chip using the UMC 90 nm process technology.

Details

ISSN :
1558173X and 00189200
Volume :
46
Database :
OpenAIRE
Journal :
IEEE Journal of Solid-State Circuits
Accession number :
edsair.doi...........f355430cb41c8bc84cbf74ef15f58e5e
Full Text :
https://doi.org/10.1109/jssc.2010.2102571