Back to Search Start Over

Error-Reduction Controller Techniques of TaOx-Based ReRAM for Deep Neural Networks to Extend Data-Retention Lifetime by Over 1700x

Authors :
Yoshiaki Deguchi
Toshiki Nakamura
Kazuki Maeda
Shun Suzuki
Ken Takeuchi
Source :
2018 IEEE International Memory Workshop (IMW).
Publication Year :
2018
Publisher :
IEEE, 2018.

Abstract

This paper proposes the ReRAM controller with three ReRAM error-reduction techniques for Deep Neural Network (DNN). The proposed ReRAM system stores the weights of DNN. The first technique, short codeword error-correcting code (ECC), reduces more errors than conventional long codeword ECC when the bit error rate (BER) is high such as over 10-2. The second technique, One Way Error Correction (OWEC), reduces miscorrection of short codeword ECC by considering data-retention characteristics of ReRAM. The third technique, One-Bit Error Correction (OBEC), is the shortest codeword ECC which reduces errors of the most significant bit of DNN weights effectively. These techniques realize high image recognition accuracy by utilizing error tolerance of DNN even for an extremely long data-retention time. As a result, the acceptable data-retention time is extended by over 1700-times compared with BCH ECC.

Details

Database :
OpenAIRE
Journal :
2018 IEEE International Memory Workshop (IMW)
Accession number :
edsair.doi...........efd563409507060ad7b4a8a8fb3891a5
Full Text :
https://doi.org/10.1109/imw.2018.8388830