A Design of 16-bit High Speed DAC with Segmented R2R Load

This paper describes a 16-bit 5GSPS high-speed DAC with segmented R2R load, using a 65nm CMOS process, and consists of a SERDES receiver, a high-speed thermometer decoder, a high-speed MUX, a high-speed data latch, a DAC core, and so on. Through the R2R load to ensure that the current density of each pair of switch is the same. The same drive unit is used for the switch input stage, which ensures that the switch changes at the same time. Switching simultaneously can improve the dynamic performance of the high speed DAC. In this paper measured performance of greater than 65 dBc SFDR is achieved at 500 MHz output signal.