Timing-reliable Design of High-speed TigerSHARC 201 Link Transceiver

TigerSHARC 201 link interface is a very efficient double data rate protocol. However, its inconsecutive characteristic of clock adds great difficulty for FPGA implementation when transmission rate is too high. In this paper, with specially-designed clock tree, ingenious rate decreasing strategy, plus proper control on FPGA place & routing processing, 8 group link transceivers with data rate over 500MB/s per lane were designed successfully on Xilinx Virtex6 XC6VLX130. Besides, no sophistic IOSERDES component was utilized. Whole design was completed via Verilog RTL code and Xilinx user constrained file. Presented design also has experienced harsh environment test, proved its efficiency and reliability.