Analog Device Design for Testability in the Case of Oscillation Based Testing

This paper aims toward joining the ideas of OBT (oscillation-based testing) and DFT (design for testability). It gives insight into an optimization process that provides testability if one chooses to use the OBT. The optimization procedure is exemplified on a timer device NE555. Utilization of a timer circuit allows avoidance of a specific design of the feed-back loop. The optimization procedure is based on the Monte Carlo analysis. Once a device Spice model is acquired with all the elements of the model designed in a certain parameter tolerance space, one can move to the optimization for testability. Total derivatives of the function of oscillation frequency due to parameters values are estimated. The point that corresponds to the maximal total derivative is chosen as the appropriate set of parameter values for DFT. After the optimization procedure described in this paper has been performed on a Spice model, one can use the model parameters to set the goals of the IC design and manufacturing process of the device.