Structural and Electrical Properties of Y2O3 Buffer Layer Prepared by Two Step Process

In this paper we investigated a feasibility of Y2O3 films as a buffer layer of MFIS (metal ferroelectric insulator semiconductor) type capacitor. Buffer layers were prepared by two-step process of a low temperature film growth and subsequent RTA treatment. Investigated parameters are given as substrate temperature, O2 partial pressure, post-annealing temperature, and suppression method of interfacial SiO2layer generation. By employing an ultra thin Y pre-metal layer, unwanted SiO2 layer generation was successfully suppressed at an interface between the buffer layer and Si substrate. By using two-step process, we improved the leakage current density of Y2O3 films by 2 orders and the Dit as low as 8.72×1010 cm−2eV−1. For a substrate temperature above 400°C and O2 partial pressure of 20%, we observed cubic Y2O3 phase domination in XRD spectra. We achieved 1.75% lattice mismatch between Y2O3 film and silicon substrate. Y2O3 buffer layer for a single transistor FRAM exhibited optimal properties when it was grown at 400°C with 20% O2 partial pressure then RTA treatment at 900°C in oxygen ambient.