Study on predicting the temperature of stacked chip based on thermal resistance matrix

In this study, a four-layer stacked chip simulation model is built under standard JEDEC environment, the heat dissipation path and temperature distribution of the stacked chip is analyzed. Based on linear superposition method, a method of estimating the temperature of stacked chip using thermal resistance matrix is proposed, and the function relationship between the power consumption and the element values of the thermal resistance matrix is established. The accuracy of the thermal resistance matrix is researched through simulation analysis, and the difference between the results of the thermal resistance matrix prediction and the simulation results is about 0.01%.