SoC Design and Implementation of CAN 2.0 Protocol Toward Satellite Applications

This paper designs and implements an IP that supports the CAN 2.0 protocol and integrates it into the designed SoC. The upper layer software can be used to control and manage the CAN protocol. The SoC that we designed in this paper adopts AHB and APB bus architecture, which can easily integrate the IP of this bus. The processor core uses a five-stage pipeline to support the ArmV4 instruction set architecture. The multiplication unit uses pipeline processing. The forwarding unit and scoreboard unit module can solve and alleviate data dependence and improve instruction execution efficiency. The design has been verified by simulation and its function is correct. The comprehensive results of the target device Spartan-7 show that the design consumes less resources and can be implemented in FPGA. The design can be used in satellite-based integrated electronic solutions of small satellite to complete data transmission and information exchange between spacecraft electronic equipment.