Fully integrated, highly linear, wideband LNA in 0.13μm CMOS technology

This paper presents the design of a fully integrated, highly linear, wideband low noise amplifier (LNA). The LNA employs a three stage distributed topology along with input and output matching networks. The transistors have been biased in weak/moderate inversion to achieve better linearity. The post-layout simulation results for the proposed design presents a bandwidth of 0.1-1.9 GHz with an IIP3 of +3.8 dBm and input referred 1-dB CP of -7.72 dBm. The LNA achieves a power gain of 10 dB, NFmin of 4.4 dB and power consumption of 65 mW. With a supply voltage of 2 V, the design has been simulated in Cadence SpectreRF, using IBM 130 nm CMOS technology. The target is to achieve a wide band low noise amplifier that would suffice for multiple standards while offering high linearity.