Development and Evaluation of a Highly Linear CMOS Image Sensor With a Digitally Assisted Linearity Calibration

This paper presents a highly linear CMOS image sensor (CIS) designed in a commercial 0.18- $\mu$ m CIS technology. A new type of pixel is proposed based on the linearity analysis of a conventional 4T active pixel. The new type of pixel can mitigate the nonlinearity caused by the in-pixel source follower (SF) transistor. In addition, the optimization of the pixel design, a digitally assisted calibration method is proposed to further reduce the nonlinearity of the image sensor, especially, the nonlinearity caused by the integration capacitor ( $C_{\mathrm {FD}}$ ) on the floating diffusion (FD) node. A hybrid behavioral model is proposed to validate the calibration method. Experimental results show that the new type of pixel has a better linearity performance comparing with that of the typical 4T pixel. TCAD simulation results are used to help explain the spillback effect in the transfer transistor’s channel. With the digital calibration, the linearity performances of the pixels in different settings have been improved.