Cite
SDP: Co-Designing Algorithm, Dataflow, and Architecture for In-SRAM Sparse NN Acceleration
MLA
Fengbin Tu, et al. “SDP: Co-Designing Algorithm, Dataflow, and Architecture for In-SRAM Sparse NN Acceleration.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, Jan. 2023, pp. 109–21. EBSCOhost, widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edsair&AN=edsair.doi...........e5783bb7e763b267078e45b7150e3890&authtype=sso&custid=ns315887.
APA
Fengbin Tu, Yiqi Wang, Ling Liang, Yufei Ding, Leibo Liu, Shaojun Wei, Shouyi Yin, & Yuan Xie. (2023). SDP: Co-Designing Algorithm, Dataflow, and Architecture for In-SRAM Sparse NN Acceleration. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 42, 109–121.
Chicago
Fengbin Tu, Yiqi Wang, Ling Liang, Yufei Ding, Leibo Liu, Shaojun Wei, Shouyi Yin, and Yuan Xie. 2023. “SDP: Co-Designing Algorithm, Dataflow, and Architecture for In-SRAM Sparse NN Acceleration.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 42 (January): 109–21. http://widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edsair&AN=edsair.doi...........e5783bb7e763b267078e45b7150e3890&authtype=sso&custid=ns315887.