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A VLSI design of hierarchical search motion estimation processor chip
- Source :
- AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360).
- Publication Year :
- 2003
- Publisher :
- IEEE, 2003.
-
Abstract
- This paper presents a motion estimation processor that has regular and simple structure and achieves 100% hardware utilization without image data fill time. It can compute half-pel precision estimation and I/O bottleneck is eliminated using a small distributed on-chip image memory. The number of processing elements is scalable according to the degree of parallel processing and throughput requirements. It has been designed and verified with C++ and VHDL.
- Subjects :
- Very-large-scale integration
business.industry
Computer science
Parallel computing
Integrated circuit design
Bottleneck
Parallel processing (DSP implementation)
Application-specific integrated circuit
Motion estimation
VHDL
business
Throughput (business)
computer
Computer hardware
computer.programming_language
Subjects
Details
- Database :
- OpenAIRE
- Journal :
- AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)
- Accession number :
- edsair.doi...........e39cad555c64558dc983085f3a7cdb26
- Full Text :
- https://doi.org/10.1109/apasic.1999.824075