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A Planar Integration Process for E/D-mode AlGaN/GaN HEMT DCFL Integrated Circuits

Authors :
Kevin J. Chen
Zhiqun Cheng
Kei May Lau
Chi-Wai Tang
Yong Cai
Ruonan Wang
Source :
2006 IEEE Compound Semiconductor Integrated Circuit Symposium.
Publication Year :
2006
Publisher :
IEEE, 2006.

Abstract

We demonstrate a new planar fabrication technology for integrating enhancement/depletion (E/D) mode AlGaN/GaN HEMTs using fluoride-based plasma treatment techniques. The CF4 plasma treatment is used in two separate steps to achieve two objectives: 1) active device isolation; and 2) threshold voltage control for the E-mode HEMT formation. By using the planar process, the E/D-mode HEMTs are integrated on the same chip, and a direct-coupled FET logic inverter and a 17-stage ring oscillator are fabricated. Compared with the devices formed by standard mesa etching, the HEMTs by planar process have comparable DC and RF characteristics, with no obvious difference in device isolation. At a supply voltage of 3.3 V, the E/D-mode inverter shows an output swing of 2.85 V, with the logic low and logic high noise margins at 0.34 and 1.47 V. The fabricated ring oscillator yields an oscillating frequency of 159 MHz at a supply voltage of 4.5 V. After a 44 hrs thermal stress at 350degC, the devices show negligible change in DC and RF characteristics, indicating excellent thermal stability of the planar process

Details

Database :
OpenAIRE
Journal :
2006 IEEE Compound Semiconductor Integrated Circuit Symposium
Accession number :
edsair.doi...........e2669c2dcfdaa419dc6f04218432692c
Full Text :
https://doi.org/10.1109/csics.2006.319949