Improvement Research of VIA Hole Minimize by Passivation Layer Deposit Conditions

In the trend of miniaturization narrow frame and fine wiring structure,the TFT-LCD tends to developing for large margin of design and high real substrate utilization rate.The passivation layer deposit parameters were changed to decrease the size of via hole which connected the pixel electrode and drain electrode were studied.Through the experiments design of changing main parameters to minimize via hole of passivation layer(haze,undercut,Top-PVX deposit thickness,Top-PVX deposit pressure),a solution to minimize the via hole about 20%~30% without changing the etch conditions was found.The electronic parameter measurement was evaluated(Ion,Ioff,Vth,Mobility) and finally one better solution to minimize via hole size was obtained.Therefore,the products quality was improved also.