Electrical and optical clock distribution networks for gigascale microprocessors

A summary of electrical and optical approaches to clock distribution within high-performance microprocessors is presented. System-level properties of intrachip electrical clock distribution networks corresponding to three microprocessor families are summarized. It is found that global clock interconnect performance and short-term jitter present the greatest challenges to the continued use of conventional clock distribution methodologies. An extrapolation of trends describing the percentage of clock period consumed by global skew and short-term jitter identifies the 32-nm technology generation of the 2002 International Technology Roadmap for Semiconductors (ITRS) as the first technology generation within which alternate methods of clock distribution may be warranted. Research efforts investigating interboard through intrachip optical clock distribution are also summarized. An optical distribution network compatible with high volume manufacturing in conjunction with a suitable means of providing optical-to-electrical signal conversion comprise the two fundamental challenges facing successful implementation of an optical clock distribution network. It is found that a global guided-wave distribution capable of efficient input and output coupling of optical power is required to meet the first challenge. The identification of a suitable means of optical-to-electrical conversion, however, remains an active topic of research.