Customized Parallel Reliability Testing Platform with Multifold Throughput Enhancement for Intel Stressing Tests

Using a typical Semiconductor Parameter Analyzer (SPA) for semiconductor reliability stress tests such as Time Dependent Dielectric Breakdown (TDDB), bias temperature instability (BTI), Hot Carrier Injection (HCI), has limitations. The SPA tends to be inflexible in dealing with concurrent multiple failure modes, managing multiple touchdown requirements, and so on. These issues can be effectively mitigated through the usage of massively parallel reliability tests. This paper presents a new Parallel Reliability Test Platform (PRTP) that has been developed and integrated at Intel Corp. with the support of Intel's test partners. The PRTP was built innovatively by integrating customized and modularized electronic hardware, new parallel probing solutions and in-house developed automation systems. It enables the capability to conduct measurements on multiple devices and/or multiple dies and demonstrates a multifold increase in throughput. This significant enhancement of industrial reliability testing throughput facilitates the collection of large data sets and sample sizes in realistic timeframes and enables Intel to release new products to the market in shorter time while maintaining robust statistical confidence.