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An Analytical Model for the Effective Drive Current in CMOS Circuits
An Analytical Model for the Effective Drive Current in CMOS Circuits
- Source :
- IEEE Transactions on Electron Devices. 66:855-860
- Publication Year :
- 2019
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 2019.
-
Abstract
- Inverter delay is often evaluated as $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ , where ${C}$ is the load capacitance, ${V}_{\text {dd}}$ is the supply voltage, and ${I}_{\text {eff}}$ is the effective drive current derived by approximating the inverter switching trajectory with a linear model. The ${I}_{\text {eff}}$ model utilizes high and low drain currents conventionally measured in wafer acceptance tests and does not require extraction of any parameters. Ease of use combined with reasonable accuracy (~15%) is the main reason for wide application of $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ delay metrics. However, $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ expression produces large errors when applied to another two important basic circuits: NAND and NOR. This is because NAND and NOR circuits contain transistor series connections not accounted for in the inverter model. In this paper, an analytical solution for the transistor series connection influence on the discharge/charge operation in NAND/NOR circuits is provided. The model for NAND/NOR effective drive current (denoted as ${I}_{\text {stack}}$ ) developed in this paper maintains simplicity of the original ${I}_{\text {eff}}$ expression. It requires only one additional measurement of the linear current. Model accuracy was assessed by comparing to extensive SPICE delay simulations of NAND and NOR circuits designed using state-of-the-art MOS technologies. Comparison results show that $\textit {CV}_{\text {dd}}/{I}_{\text {stack}}$ equation provides ~15% accuracy for NAND/NOR circuits in line with $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ accuracy for inverter. In an era of emphasis on low-power design, the developed model presents convenient means of exploring design space when optimizing circuit supply voltage for low-power operation.
- Subjects :
- 010302 applied physics
Discrete mathematics
Physics
Series (mathematics)
Transistor
NAND gate
Charge (physics)
Series and parallel circuits
01 natural sciences
Capacitance
Electronic, Optical and Magnetic Materials
law.invention
CMOS
law
0103 physical sciences
Hardware_INTEGRATEDCIRCUITS
Electrical and Electronic Engineering
Hardware_LOGICDESIGN
Stack (mathematics)
Subjects
Details
- ISSN :
- 15579646 and 00189383
- Volume :
- 66
- Database :
- OpenAIRE
- Journal :
- IEEE Transactions on Electron Devices
- Accession number :
- edsair.doi...........d8f9deeb9f45a07a60cdc8a25c653f90
- Full Text :
- https://doi.org/10.1109/ted.2018.2885806