NVMain 2.0: A User-Friendly Memory Simulator to Model (Non-)Volatile Memory Systems

Authors :: Tao Zhang
Yuan Xie
Matthew Poremba
Source :: IEEE Computer Architecture Letters. 14:140-143
Publication Year :: 2015
Publisher :: Institute of Electrical and Electronics Engineers (IEEE), 2015.
Abstract: In this letter, a flexible memory simulator - NVMain 2.0, is introduced to help the community for modeling not only commodity DRAMs but also emerging memory technologies, such as die-stacked DRAM caches, non-volatile memories (e.g., STT-RAM, PCRAM, and ReRAM) including multi-level cells (MLC), and hybrid non-volatile plus DRAM memory systems. Compared to existing memory simulators, NVMain 2.0 features a flexible user interface with compelling simulation speed and the capability of providing sub-array-level parallelism, fine-grained refresh, MLC and data encoder modeling, and distributed energy profiling.

Subjects :: 010302 applied physics
Hardware_MEMORYSTRUCTURES
Computer science
Sense amplifier
Registered memory
02 engineering and technology
01 natural sciences
Memory map
Memory controller
020202 computer hardware & architecture
Computer architecture
Hardware and Architecture
0103 physical sciences
0202 electrical engineering, electronic engineering, information engineering
Interleaved memory
Non-volatile random-access memory
Memory rank
Memory refresh
Simulation

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