Cite
Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC Server on a Chip
MLA
King C. Yen, et al. “Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC Server on a Chip.” IEEE Journal of Solid-State Circuits, vol. 43, Jan. 2008, pp. 6–20. EBSCOhost, widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edsair&AN=edsair.doi...........d30300acb31dce6ba2b28f6781cd06c8&authtype=sso&custid=ns315887.
APA
King C. Yen, Amit Kumar, David J. Greenhill, Umesh Gajanan Nawathe, Mahmud Hassan, & Aparna Ramachandran. (2008). Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC Server on a Chip. IEEE Journal of Solid-State Circuits, 43, 6–20.
Chicago
King C. Yen, Amit Kumar, David J. Greenhill, Umesh Gajanan Nawathe, Mahmud Hassan, and Aparna Ramachandran. 2008. “Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC Server on a Chip.” IEEE Journal of Solid-State Circuits 43 (January): 6–20. http://widgets.ebscohost.com/prod/customlink/proxify/proxify.php?count=1&encode=0&proxy=&find_1=&replace_1=&target=https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&scope=site&db=edsair&AN=edsair.doi...........d30300acb31dce6ba2b28f6781cd06c8&authtype=sso&custid=ns315887.