Impact of gate current on first order parameter extraction in sub-0.1 μm CMOS technologies

MLA

A. Dray, et al. “Impact of Gate Current on First Order Parameter Extraction in Sub-0.1 Μm CMOS Technologies.” International Conference on Microelectronic Test Structures, 2003, Dec. 2003. EBSCOhost, https://doi.org/10.1109/icmts.2003.1197433.

APA

A. Dray, Nicolas Planes, H. Brut, & E. Robilliart. (2003). Impact of gate current on first order parameter extraction in sub-0.1 μm CMOS technologies. International Conference on Microelectronic Test Structures, 2003. https://doi.org/10.1109/icmts.2003.1197433

Chicago

A. Dray, Nicolas Planes, H. Brut, and E. Robilliart. 2003. “Impact of Gate Current on First Order Parameter Extraction in Sub-0.1 Μm CMOS Technologies.” International Conference on Microelectronic Test Structures, 2003, December. doi:10.1109/icmts.2003.1197433.