Power efficient low latency architecture for decoder: Breaking the ACS bottleneck

Subjects

Subjects :

Maximum likelihood algorithm
Computer science
Applied Mathematics
Power efficient
Parallel computing
Electrical and Electronic Engineering
Architecture
Latency (engineering)
Bottleneck
Computer Science Applications
Electronic, Optical and Magnetic Materials

Details

ISSN :

1097007X and 00989886

Volume :

47

Database :

OpenAIRE

Journal :

International Journal of Circuit Theory and Applications

Accession number :

edsair.doi...........d186c4b955476ac94c6d02cd1768832e

Full Text :

https://doi.org/10.1002/cta.2663