Back to Search
Start Over
A NoC-based simulator for design and evaluation of deep neural networks
- Source :
- Microprocessors and Microsystems. 77:103145
- Publication Year :
- 2020
- Publisher :
- Elsevier BV, 2020.
-
Abstract
- The astonishing development in the field of artificial neural networks (ANN) has brought significant advancement in many application domains, such as pattern recognition, image classification, and computer vision. ANN imitates neuron behaviors and makes a decision or prediction by learning patterns and features from the given data set. To reach higher accuracies, neural networks are getting deeper, and consequently, the computation and storage demands on hardware platforms are steadily increasing. In addition, the massive data communication among neurons makes the interconnection more complex and challenging. To overcome these challenges, ASIC-based DNN accelerators are being designed which usually incorporate customized processing elements, fixed interconnection, and large off-chip memory storage. As a result, DNN computation involves large memory accesses due to frequent load/off-loading data, which significantly increases the energy consumption and latency. Also, the rigid architecture and interconnection among processing elements limit the efficiency of the platform to specific applications. In recent years, Network-on-Chip-based (NoC-based) DNN becomes an emerging design paradigm because the NoC interconnection can help to reduce the off-chip memory accesses while offers better scalability and flexibility. To evaluate the NoC-based DNN in the early design stage, we introduce a cycle-accurate NoC-based DNN simulator, called DNNoC-sim. To support various operations such as convolution and pooling in the modern DNN models, we first propose a DNN flattening technique to convert diverse DNN operation into MAC-like operations. In addition, we propose a DNN slicing method to evaluate the large-scale DNN models on a resource-constraint NoC platform. The evaluation results show a significant reduction in the off-chip memory accesses compared to the state-of-the-art DNN model. We also analyze the performance and discuss the trade-off between different design parameters.
- Subjects :
- Interconnection
Contextual image classification
Artificial neural network
Computer Networks and Communications
Computer science
020208 electrical & electronic engineering
Pooling
02 engineering and technology
Energy consumption
020202 computer hardware & architecture
Application-specific integrated circuit
Artificial Intelligence
Hardware and Architecture
Scalability
0202 electrical engineering, electronic engineering, information engineering
Software
Simulation
Subjects
Details
- ISSN :
- 01419331
- Volume :
- 77
- Database :
- OpenAIRE
- Journal :
- Microprocessors and Microsystems
- Accession number :
- edsair.doi...........cec98b640850c6db6079ab131d4eca83