Low power nonvolatile SRAM circuit with integrated low voltage nanocrystal PMOS Flash

This paper presents a new nonvolatile SRAM design that incorporates low-voltage nanocrystal PMOS Flash transistors. The design enables global store, restore and erase operations with negligible penalty on regular SRAM operation. Store/erase operations also do not consume much power even considering charge pump circuits. Circuit simulations based on experimental I–V characteristics demonstrate that 10 µs store/erase operation at ± 6 Vis sufficient for correct restoration of the stored bit even under reasonable process variation.