A Novel Ultra Low Power Accuracy Configurable Adder at Transistor Level

Low power consumption, nowadays, has emerged to be an indispensable factor as there is a growing demand for designing efficient computation-intensive systems and integrating more transistors on chips. With a trade-off between area, delay, power consumption, and accuracy, approximate computing has become a promising solution to address the power efficiency problem for error-tolerant applications such as digital signal processing. Adders are imperative arithmetic components in the applications above. As adder participates in the critical path of most systems, reducing the power consumption of them can contribute to the total system power efficiency. To achieve high flexibility and less fault occurrence when using approximate computation, reconfigurable addition can be beneficial by providing different modes of approximate and accurate operations in multi-bit adder circuits. In this paper, we propose a 16-transistor accurate full adder design based on a 10-transistor full adder for which the threshold loss problem, has been reduced to increase the output voltage swing. This 16-transistor full adder is our baseline for the further proposed configurable bimodal design, which functions as a Lower-part-OR (LOA) Adder in the approximate mode. Having been optimized at transistor level, this configurable bimodal full adder, in the approximate mode, consumes 53% lower power than LOA adder. Moreover, in the accurate mode, the power consumption is reduced by 12% compared to its baseline 16-transistor accurate design.