A 12-b, 60-MSample/s cascaded folding and interpolating ADC

The architecture of this 12 b ADC is based on a three-stage conversion, using cascaded folding and interpolating techniques. Compared to other multi-stage ADC architectures, folding and interpolating ADCs are based on non-linear analog pre-processing. This architecture is an attractive solution for high-resolution ADCs, as extremely linear circuit topologies are not required. To increase the resolution of folding and interpolating ADCs above the published 8 b examples, without raising the number of parallel input stages or the number of comparators in the fine-comparator, a cascaded folding and interpolating architecture is introduced. The ADC achieves 64 dB signal-to-noise ratio (SNR) and 75 dB spurious-free dynamic range (SFDR), while quantizing a 15 MHz full-scale input signal at 50 MSample/s. The 7.0 mm/sup 2/ ADC is fabricated in a 13 GHz, 1 /spl mu/m BiCMOS process and dissipates 300 mW from a single 5.0 V supply. The device is mounted in a standard 44-pin plastic package.