Performance Modeling and Bottleneck Analysis of EDGE Processors Using Dependence Graphs

Exploring new directions in ISA and microarchitecture design can be challenging due to the large search space. Efficient tools and methods are needed to quickly identify rewarding design choices. In this work, we develop a graph-based framework that effectively models complex architectures and enables efficient analysis of their performance and bottlenecks. We use this framework to investigate proposals for EDGE (Explicit Data Graph Execution) ISA, a new class of ISA in which programs are composed from atomic blocks, each of which explicitly exposes dataflow to hardware. We study the impact of two important EDGE-specific design choices: block formats and operand-movement instructions. We demonstrate how this analysis leads to insights in EDGE architectures.