A Cell-Based Fractional-N Phase-Locked Loop Compiler

In this work, we present the first cell-based Fractional-N Phase-Locked Loop (PLL) compiler, according to the best of our knowledge. Unlike its previous integer-N PLL compiler, a target clock frequency can be generated precisely with an almost arbitrary input reference clock frequency. For example, 1 GHz output clock can be generated from a given 17.33MHz reference clock. With a search engine, such a compiler can find a small-area as well as low-power PLL configuration within minutes. We also have verified its ability for two process nodes (i.e., 90nm and 180nm) by transistor-level simulation on seven test-case PLL macros generated by this compiler. Experimental results show that they can indeed function correctly under extreme PVT conditions.