Behaviour of fractional loop delay zero crossing digital phase locked loop (FR-ZCDPLL)

This paper analyze the performance of the first-order zero crossing digital phase locked loops (FR-ZCDPLL) when fractional loop delay is added to loop. The nonlinear dynamics of the loop is presented, analyzed, and examined through bifurcation behaviour. Numerical simulation of the loop is conducted to proof the mathematical analysis of the loop operation. The results of the loop simulation show that the proposed FR-ZCDPLL has enhanced the performance compared to the conventional Zero Crossing DPLL (C-ZCDPLL) in terms of wider lock range, captured range and stable operation region. In addition, extensive experimental simulation was conducted to find the optimum loop parameters for different loop environmental conditions. The addition of the fractional loop delay network in the conventional loop also reduces the phase jitter and its variance especially when the Signal to Noise Ratio (SNR) is low.