Back to Search
Start Over
Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper)
- Source :
- ICCAD
- Publication Year :
- 2017
- Publisher :
- IEEE, 2017.
-
Abstract
- As the complexity and scale of circuits keep growing, clocking architectures of FPGAs have become more complex to meet the timing requirement. In this paper, to optimize wirelength and meanwhile meet emerging clocking architectural constraints, we propose several detailed placement techniques, i.e., two-step clock constraint legalization and chain move. After integrating these techniques into our FPGA placement framework, experimental results on ISPD 2017 benchmarks show that our proposed approach yields 2.3% shorter routed wirelength and the running time is 2x faster compared to the first place winner in the ISPD 2017 contest. Moreover, we explore the possibilities to use machine learning-based methods to predict routing congestion in UltraScale FPGAs. Experimental results on both ISPD 2016 and ISPD 2017 benchmarks show that our proposed congestion estimation model is a good approximation to the one obtained from Vivado and can lead to good placement results compared to the previous methods.
- Subjects :
- Computer science
business.industry
0211 other engineering and technologies
02 engineering and technology
Machine learning
computer.software_genre
020202 computer hardware & architecture
Hardware_INTEGRATEDCIRCUITS
0202 electrical engineering, electronic engineering, information engineering
Artificial intelligence
Field-programmable gate array
business
computer
021106 design practice & management
Electronic circuit
Subjects
Details
- Database :
- OpenAIRE
- Journal :
- 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
- Accession number :
- edsair.doi...........bffb7366619415a7f5ac95823774c388